With the advent of the computer age, electronic systems have become a staple of modern life. Part and parcel with this spread of technology comes an ever greater drive for more functionality from these electronic systems. A microcosm of this quest for increased functionality is the size and capacity of various semiconductor devices. From the 8 bit microprocessor of the original Apple I, through the 16 bit processors of the original IBM PC AT, to the current day, the processing power of semiconductors has grown while the size of these semiconductors has consistently been reduce. In fact, Moore's law recites that the number of transistors on a given size piece of silicon will double every 18 months.
As semiconductors have evolved into these complex systems utilized in powerful computing architectures, almost universally, the frequency at which these semiconductors devices operate has been increasing. These modern high-performance systems are designed with a target clock frequency. The clock frequency determines the processing speed of the system.
The continuous quest for higher semiconductor performance has pushed clock frequencies deep into the gigahertz frequency range, reducing the period of the clock signal well below a nanosecond. As the working frequency of advanced semiconductor systems has entered the gigahertz domain, designing clock distribution networks for these semiconductor devices becomes much more challenging.
Clock distribution networks are used to distribute a clock signal to the circuits on a semiconductor device that require that clock. An embodiment for one methodology for distributing clock signals within a semiconductor device, known as a clock distribution tree is depicted in FIG. 1. A clock signal may be produced by a phase locked loop (PLL) 110 on semiconductor device 100. Areas 120, 130 on semiconductor device 100 may utilize the clock signal produced by PLL 110. Thus, the clock signal produced by PLL 110 may be distributed to areas 120, 130 by a clock distribution tree. As clocks are used to drive processors or to synchronize the data distribution between or among gates or circuits in areas 120, 130, design of these clock distribution networks have become an important part of semiconductor design.
In particular, clock skew, which is defined as the time difference between clock transitions within a system, can have a large impact on the overall performance of a semiconductor. As speeds are increasing, clock periods are getting shorter, and, hence, skews are becoming more of a problem. The primary objective of a clock distribution tree is therefore to minimize the signal skew at sinks with minimal phase delay, wire length, area and power consumption. Deviations of the clock signal produced by PLL 110 from a target delay can cause incorrect data to be latched within a register in areas 120 or 130, resulting in the malfunction of semiconductor 100. These deviations of the delay of a signal from a target value are described as delay uncertainty. The uncertainty of the clock signal delay is caused by a number of factors that affect a clock distribution tree, examples of which include process and environmental parameter variations. Effects such as the non-uniformity of the gate oxide thickness and imperfections in the polysilicon etching process can cause variations in the current flow within a transistor, thereby introducing delay uncertainty. In addition, variations in the geometric parameters of the interconnect wires introduce uncertainty in the signal characteristics.
More specifically, the length of the clock distribution tree between PLL 110 and areas 120, 130 introduces signal delay. Inserting buffers along an interconnect line in the clock distribution tree between PLL 110 and areas 120, 130 may help alleviate the dependence of the signal propagation delay on the line length of clock distribution tree between PLL 110 and areas 120, 130, permitting an interconnect line between PLL 110 and areas 120, 130 to behave more akin to a simple capacitive line.
Typically, clock buffers are inserted in a bottom-up approach, starting from the leaves of the clock distribution tree (i.e. the clocked elements) at the lowest level and advancing towards the root of the clock distribution tree. When an intermediate node in the tree is reached, the total load from that node to the bottom of the clock distribution tree is the summation of the capacitive load of the interconnect lines and the clocked elements which exist from that node to the bottom of the clock distribution tree. The magnitude of this downstream load may determine the size of the inserted buffer.
FIG. 2 represents one embodiment of the semiconductor device of FIG. 1 with buffers inserted in the clock distribution tree. Buffers 250, 260 are utilized in conjunction with the clock distribution tree in order to distribute a clock generated by PLL 210 to clocked elements in areas 220, 230 and any clocked elements downstream of these areas 220, 230.
One embodiment of a circuit suitable for implementing buffers 250, 260 is presented in FIG. 3. A clock signal is input to inverter 310 which drives the clock signal through the clock distribution tree to downstream logic 320, including clocked elements. Thus, circuit 300 may drive the clock signal into capacitance load C of logic 320. Suppose, however, the capacitance load of the logic into which buffer 260 is driving a signal is half the capacitance load of the logic into which buffer 250 is driving a signal. In this case, the inverter of buffer 260 may be half the strength of the inverter of buffer 250. This means that the input impedance of buffer 260 may be roughly half of that of buffer 250. In order for buffers 250, 260 to be more effective, however, ideally buffers 250, 260 would be easy to implement, and have the same input impedance in order to achieve the same timing signal propagation while simultaneously having different output driveability to optimize power consumption.
Thus, a need exists for circuits which have substantially equal propagation delay and timing skew where these circuits are operable to provide different drive strengths.